REUSABLE SOFTWARE COMPONENTS FOR REUSABLE HARDWARE DESIGNS In the 1960's and 70's, the logic of integrated circuits (ICs) was designed via gate level drawings, in accordance with higher level block diagrams of architectural ideas, usually prepared with pencil and paper. These schematics of the connections of different gates proved inadequate as devices became more and more complex. It was recognized that a high level approach would: 1) support top down design 2) support standardized reuse of components of the design 3) assist in the simulation and testing of the device 4) assist in the manufacturing process DoD's Tri-Service Very High Speed Integrated Circuit (VHSIC) program contracted for the development of sets of ICs for specific application domains of interest to the DoD. The initial sets of contracts were for the development sets of 25 MHz CMOS Large Scale Integrated Circuits (LSICs). This program included some computer simulation of the functionality of several of the chips, after the engineers had completed their design checks and considered the designs ready for fabrication of the first wafers. They were surprised to learn that these computer simulations uncovered design flaws which would have rendered the chips unusable, and would have required time consuming and expensive design and fabrication iterations to correct. The computer simulation had demonstrated that at the state-of-the-art level of complexity that was being attempted (much less than that of current devices), the previous manual methods of design verification prior to fabrication were no longer adequate. The most cost effective and efficient means to design these more complex chips would henceforth require support via computer simulation. This was the proximate cause of the decision to develop the VHSIC Hardware Description Language, VHDL [1]. At about this time, Ada was young, and there was an idea of using Ada in the early stages of the design of a system without regard to which parts would eventually become custom hardware, and which would stay software. It was hoped that the custom hardware parts could be generated by an automated process from the initial Ada text (an idea that is still appealing). In 1980, however, it was concluded at the VHSIC conference in Woods Hole that Ada was inadequate for use as a HDL even though no Ada compiler was yet available, and Ada capabilities could not yet be properly evaluated . VHDL, although using Ada as a base, was therefore developed with additional constructs that are incompatible with Ada, and which prevent it from being executable (as we execute an Ada program). VHDL as well as Verilog, the other commonly used HDL, are NOT programming languages; both are used only for the chip design. Tools input the designs generated by these languages and do analysis, simulation and testing. There are also synthesis tools that run before the final logic simulation tools and layout tools that calculate line length capacitive loadings, etc. and provide data for back annotation of the design for more precise re-simulation. These simulations are also used to develop more or less optimized sets of test vectors that are used in functional testing (screening) of the ICs which will ultimately be produced. WITH VHDL/VERILOG: ----------------------------------------------------------------- Tasks Outputs Design phase in HDL ---> logic statements, HDL syntax Synthesis tools ---> logic optimizations and vendor specific gate level implementations Simulation tools ---> logic correctness tests, up to detailed circuit level simulations # Layout tools ---> floor plan, mask layouts # Layout details must be available for circuit level simulations. ----------------------------------------------------------------- The tools, which are used to reiterate the design process, are generally written in C or C++. We emphasis, tools written in a programming language are necessary to both analyze and test the HDL design before it is agreed upon, and then to translate the design to control manufacturing. If constructs of the HDL are changed, then the tools frequently require updates. Even at the present time, not all tools support all of the constructs of the HDLs. Our experience [2] has shown that a kernel of Ada constructs is sufficient for the design of hardware components. With timing, simulation, and testing tools written in a reliable kernel of Ada constructs, the repeated iteration between design and testing can be seamless. Indeed, even synthesis and layout can be simplified, since Ada can be used to specify the design down to the gate level. And, obviously, the process will be more reliable than at present, since even Ada95 is more reliable that C or C++, and our recommended Ada kernel for this application area eliminates basically those constructs targeted by the high integrity Ada people, specifically by Barnes[3], and by Annex H of the Safety and Security Real Time Annex[4]. With an Ada Kernel: ----------------------------------------------------------------- Tasks Outputs Design phase in Ada ---> logic statements, Ada syntax ---> implementations, Ada syntax a: logic statements b: connected gate level library units ---> implementation correctness tests, Ada syntax * Layout tools ---> floor plan, mask layouts # Simulation tools ---> detailed circuit level simulations * Currently accept only Verilog/VHDL inputs, translation required. # Layout details must be available for circuit level simulations. --------------------------------------------------------------------- Although timing is becoming a more and more critical part of device design, constructs that support timing specification need not be part of an HDL, but can be incorporated into application specific tools. The clock period should be viewed as variable. A good design should accommodate the maximum clock speed within some safety margin. Timing tolerances can be established by measuring large enough samples in each production lot. Ada is uniquely qualified for this application area. Its strong constructs in support of the reuse process, such as packages and generics, will enable the creation of Intellectual Property (IP) of reliable hardware designs. The Ada Community must unite in proposing a set of Ada tools to assist in the design process and in approaching device manufacturers with a coherent plan. My thanks to the Working Group on Ada as a HDL for their assistance on this column: Sy Wong, Thomas A. Panfil, J.C. Morrison, Stephen Michell, Col. Kevin Cogan and John McCormick. 1] IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1993. Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017, USA. 2] Wong, S. Levine, G. Kernel Ada to Unify Hardware and Software Design, SIGAda '98, Washington, D.C. 11/98 from pp.28. Unfortunately, this paper (and its reprint in Ada Letters) was inadvertently abridged. For the full version, as well as sample code, a listing of the suggested Ada kernel, etc. see http://alpha.fdu.edu/~levine/wong. 3] Barnes, J. (1997), High Integrity Ada, the SPARK Approach, Addison-Wesley, England. 4] 1SO/IEC 8652 (1995), Annex H.4 Safety and Security Restrictions