with HDL;
generic
  n: positive;
package REGISTER is

  type device_state is limited private;
  type device is
  record
    data_in, data_out: HDL.bus(0..n-1):= (0..n-1 => FALSE);
    clock: HDL.input:= FALSE;
    state: device_state;
  end record;
  procedure update (d: in out device);
private
  type device_state is
  record
    clock: HDL.input:= FALSE;
  end record;
end REGISTER;