School of Computer Sciences and Engineering

 

ENGR/EGTG 2286 Digital System Design                                                 Spring 2005

 

2004-2006 Undergraduate Studies Bulletin Description:

Binary codes, gates and flip-flops, registers and counters, adders and ALUs. Analysis

and design of combinational and sequential circuits. Logic simulation. Logic families. Integrated laboratory experience.           

Prerequisites: None

 

Textbook(s):   Mano M. and Kime C, “Logic and Computer Design Fundamentals”,

3rd Edition, Prentice-Hall, 2004

 

Course objectives and outcomes:

Objective 1: To analyze and design combinational logic circuits

Outcome 1.1: Perform decimal/binary number conversion. Add binary numbers. Gain familiarity with binary codes.  

Outcome 1.2: Understand the concepts of Boolean algebra, Logic Functions and Truth Tables. Simplify Boolean expressions using K-maps.

Outcome 1.3: Design combinational circuits using gates, programmable logic, multiplexers and adders.. 

Objective 2: To analyze and design sequential logic circuits

Outcome 2.1: Understand basic flip-flop circuits (SR, D and JK) and difference between asynchronous and synchronous operation.

Outcome 2.2: Use state tables, state diagrams and K-maps to analyze and design sequential circuits with gates and flip-flops.        

Outcome 2.3: Implement sequential circuits with adders and flip-flops. Apply analysis and design techniques to ripple and synchronous counters.

 

Course Syllabus:

Week(s)          Topics                                                             Text Readings

1                        Digital and Computer Systems Overview,          Ch. 1: Sec. 1-1 to 1-7

Number Systems, Addition and Subtraction

Binary Codes.

 

2, 3                   Boolean Algebra, Logic Functions,                      Ch. 2: Sec. 2-1 to 2-3

Truth Tables, Standard Forms of Functions.

 

4, 5                   Minimization using K-maps,                                Ch. 2: Sec. 2-4 to 2-5

                        Other gates – NAND, NOR, XOR                     Ch. 2: Sec. 2-6 to 2-10

                        QUIZ 1

 

6                        Introduction to Combinational Circuit Design.    Ch. 3: Sec. 3-1 to 3-5

 

7, 8                   Programmable Logic – ROM, PLA, PAL,          Ch. 3: Sec. 3-6 to 3-7

Design with Decoders, Multiplexers                    Ch. 4: Sec. 4-1 to 4-6,

and Programmable Logic                                               and 4-9

 

9                      Arithmetic Functions – Adder, Subtractor           Ch.5: Sec. 5-1 to 5-6

and Multiplier Circuits                                       and 5-9           

QUIZ 2

 

10, 11               Flip-flops (SR, D types),                                     Ch. 6: Sec. 6-1 to 6-4

Sequential Circuit Analysis.

 

12, 13               JK Flip-flops, Design of Sequential Circuits.        Ch. 6: Sec. 6-5 to 6-6

                                                                                                            and 6-9

 

14                     Ripple and Synchronous Counters                      Ch. 7: Sec. 7-6

                                                                                                (starting on Page 331)

 

15                     FINAL EXAM

 

Course Grading:        Quiz 1                                                  20 %

                                    Quiz 2                                                  20 %

                                    Final Exam                                         30 %

                                    Labs, Assignments, Participation      30 %

 

Instructor:                  Prof. Howard Silver

                                    Room: M 114

Telephone:  (201) 692-2830

Office Hours:  Tues., Wed., Thurs. 4-5pm & other times by appointment 

Email: silver@fdu.edu

 

On-line Course Support:       

Course material and assignments are available on Blackboard,

at http://webcampus.fdu.edu. A webmail account is required.

 

Homework Problems:

Note: The problems below are all from the Mano/Kime text and are highly recommended. Underlined problems may be submitted for extra credit. The remaining problems have solutions posted on the textbook author=s website http://www.writphotec.com/mano/

 

Chapter 1 - Problems 4, 5, 9, 16(a), 22, 23

Chapter 2 - Problems 1, 6, 7, 9, 13, 15, 19, 21(a), 22(a), 24, 25

Chapter 3 - Problems 11, 12, 13, 15, 17

Note: For Prob. 12, try to use XOR gates and logic sharing.

Chapter 4 - Problems 10, 21, 24, 25

Note: For Prob. 24, use variable A as the input instead of D (to conform to class notation).

Chapter 5 - Problems 4, 8(a)

Note: For Prob. 8(a), use XOR=s where possible.

Chapter 6 - Problems 5, 6, 8, 14

Note: For Prob. 14, repeat the design using JK flip-flops.

Chapter 7 - Problems 14, 17, 18

Note: For both Prob. 17 and 18, repeat the design using JK flip-flops.